1. Field of the Invention
This invention relates generally to the field of data processing systems, and particularly to an apparatus for latching an address from a multiplexed address/data bus and automatically incrementing the address.
2. Background Art
Most present day personal and workstation computers are organized as shown in FIG. 1. A central processing unit (CPU) 10 is coupled to a local CPU bus 12 as is the main memory 14. A cache memory 16 may also be coupled to bus 12. Communication with peripheral devices 22 is accomplished over an expansion bus 20 coupled to I/O port 18. A number of expansion bus standards have been developed. One such standard is the industry standard architecture (ISA) bus that is widely used in personal computer systems. More recently, the extended ISA (EISA) bus has been developed. This is a superset of the ISA bus that includes all ISA bus features, together with extensions to enhance system performance and capabilities. Both the ISA bus and EISA bus have relatively narrow bandwidths in comparison to the bandwidth available on local busses for state-of-the-art high performance CPUs. This results in I/O bottlenecks and limits the ability of the system to service high performance peripherals such as local area network (LAN), SCSI, graphics and video.
In order to deal with the inherent limitations of earlier generation expansion bus standards, a new bus standard designated the "Peripheral Component Interconnect" (PCI) bus has been developed. PCI is a fast local bus particularly adapted for servicing high performance peripheral units. A typical system employing a PCI bus is illustrated in FIG. 2. A PCI/cache memory controller (PCMC) 30 provides a bridge between the host CPU 10 and the PCI bus 32. The PCMC integrates the cache and main memory DRAM control function and provides the bus control for transfers between the CPU 10, cache 16, main memory 14 and the PCI bus. The PCMC is used in conjunction with a local bus accelerator (LBX) 31 which provides the host to PCI address path and data paths between the CPU/cache, main memory and PCI bus. The LBX also contains posted write buffers and read-prefetch buffers. Together, the PCMC and LBX provide a full function data path to main memory and form a PCI bridge to the host subsystem (CPU/cache).
During PCI-to-main memory cycles, the PCMC/LBX acts as a target on the PCI bus, allowing PCI masters to read from and write to main memory. During CPU cycles, the PCMC acts as a PCI master. The CPU can then read and write I/O, memory and configuration spaces on the PCI. The PCI bus operates in a multiplexed, burst mode, with transfers comprising an address phase followed by multiple data word phases.
PCI-to-main memory cycles invoke a main memory chip select (MEMCS#) signal. When asserted, MEMCS# indicates to the PCMC that a PCI master cycle is targeting main memory. MEMCS# is generated by the PCEB (described below) and is sent to the PCMC on a dedicated line.
In order to maintain system compatibility with peripheral units designed to operate with earlier generation ISA/EISA expansion busses, a PCI/expansion bus bridge unit 40 is coupled between the PCI bus and the ISA or EISA expansion bus 20. A system such as shown in FIG. 2 is thus able to take advantage of the increased performance capabilities of the PCI bus while maintaining access to the large existing base of ISA and EISA expansion cards and their corresponding software applications.
The PCI bus is particularly designed to address the growing need for a standardized local bus that is not directly dependent on the speed and size of the CPU bus. New generations of personal computer system software with sophisticated graphical interfaces, multi-tasking and multi-threading bring new requirements that traditional PC input/output architectures cannot satisfy. As indicated in FIG. 2, the input/output functions of the system are decoupled from the processor and memory assets, thereby enabling the input/output design of the system to remain stable over multiple generations of processor and/or memory technology. Regardless of new requirements or technology applied on the CPU side of the host bridge, the PCI side may remain unchanged, which allows re-usability of not only the remainder of the platform chip set, including the PCI/expansion bus bridge, but also all of the other I/O functions interfaced at both the PCI and expansion bus levels.
The PCI/expansion bus bridge unit 40 integrates several bus functions on both the PCI and expansion busses. For the PCI local bus, the functions include PCI local bus arbitration and default bus driver. In the case of an EISA expansion bus, the central functions include the EISA bus controller, EISA arbiter and EISA data swap logic. The PCI/EISA bridge also integrates system functions, including PCI parity and system error reporting, buffer coherency management protocol, PCI and EISA memory and I/O address mapping and decoding. For maximum flexibility, all of these functions are programmable, thereby allowing for a variety of optional features. A particular PCI/EISA bridge set has been developed for the Intel Pentium.TM. processor. This chip set is illustrated in FIG. 3 and comprises a PCI/EISA bridge (PCEB) and a EISA system component (ESC). These two components work in tandem to provide an EISA I/O sub-system interface for personal computer platforms based on the Pentium.TM. processor chip and PCI bus standard. A corresponding chip set for the PCMC/LBX has also been developed for the Pentium.TM. processor.
The hierarchy of the CPU bus as the execution bus, PCI local bus as a primary I/O bus and EISA bus as a secondary I/O bus allows concurrency for simultaneous operations in all three bus environments. Data buffering permits concurrency for operations that cross over from one bus environment to another. For example, a PCI device may post data into the PCEB, permitting the PCI local bus transaction to complete in a minimum time and freeing up the PCI local bus for further transactions. The PCI device need not wait for the transfer to complete to its final destination. Meanwhile, any ongoing EISA bus transactions are permitted to complete. The posted data will then be transferred to its EISA bus destination when the EISA bus is available. The PCEB-ESC chip set implements extensive buffering for PCI-to-EISA and EISA-to-PCI bus transactions. In addition to concurrency for the operation of the cross-bus environments, data buffering allows advantage to be taken of the fastest operations within a particular bus environment via PCI burst transfers and EISA burst transfers.
The PCI local bus with 132 MByte/second and EISA with 33 MByte/second peak data transfer rates represent bus environments with significantly different bandwidths. Without buffering, transfers that cross between bus environments would be performed at the speed of the slower bus. Data buffers provide a mechanism for data rate adoption so that the usable bandwidth of the fast bus environment (PCI) is not significantly impacted by the slower bus environment (EISA).
The PCEB can be either a master or slave on the PCI local bus and it is optimized for bus frequencies from 25 megahertz to 33 megahertz. For PCI-initiated transfers, the PCEB functions only as a slave. For EISA-initiated transfers to the PCI local bus, the PCEB is a PCI master. The PCEB contains a fully EISA-compatible master and slave interface. The PCEB directly drives eight EISA slots without external data or address buffering. The PCEB functions as a master or slave on the EISA bus only for transfers between the EISA bus and PCI local bus. For transfers confined to the EISA bus, the PCEB functions neither as a master nor slave. However, the data swap logic contained in the PCEB is involved in such transfers if data size translation is required.
The ESC implements system functions, such as timer/counter, DMA, and interrupt controller. The ESC also implements EISA sub-system control functions, such as EISA bus controller and EISA bus arbiter.